Exception Handling for Device Compilers

  • Article

9/7/2007

Exception handling works differently on RISC-based microprocessors (such ARM, SH-4, and MIPS) than on x86 microprocessors. Under many circumstances, the compiler hides the differences; however, the differences become critical when your code contains assembly language segments.

In simplified terms, in an x86 environment, the data structures associated with exception handling are written onto the stack at runtime. The OS looks at these structures to locate appropriate exception-handling routines.

In a RISC environment, many data structures associated with exception handling are calculated at compile time and are written to the data sections of the module being built. RISC-based microprocessors support a table-based mechanism using PDATA Structures to handle exception processing that depends on the context, the frame and stack pointers, and the program counter. Because the compiler generates the code segments that set up the stack frame whose address limits are associated with the function table entry, only code that the compiler handles can access the table entry automatically.

Therefore, in a RISC environment, you must write code that manages exception-related processing for any assembly code functions you include.

In This Section

  • SEH in x86 Environments
    Provides a brief description of how exception handling works in an x86 processor environment.
  • SEH in RISC Environments
    Provides a brief description of how exception handling works in a RISC processor environment.
  • PDATA Structures
    Provides reference information about data structures used in RISC exception handling.
  • ARM Prolog and Epilog
    Provides guidelines and examples for creating prolog and epilog code sequences for ARM microprocessor compilers.
  • MIPS Prolog and Epilog
    Provides guidelines and examples for creating prolog and epilog code sequences for MIPS microprocessor compilers.