Registers - vs_2_0

This section contains reference information for the input and output registers implemented by vertex shader version 2_0.

Input Registers

Register Name Count R/W # Read ports # Reads / inst Dimension RelAddr Defaults Requires DCL
v# Input Register 16 R 1 Unlimited 4 No See note 1 Yes
r# Temporary Register 12 R/W 3 Unlimited 4 No None No
c# Constant Float Register See note 2 R 1 2 4 a0 / aL (0, 0, 0, 0) No
a0 Address Register 1 R/W 1 2 4 No None No
b# Constant Boolean Register 16 R 1 1 1 No FALSE No
i# Constant Integer Register 16 R 1 1 4 No (0, 0, 0, 0) No
aL Loop Counter Register 1 R 1 2 1 No None No

 

Notes:

  1. Partial (0, 0, 0, 1) - If only a subset of channels are updated, the remaining channels will default to (0, 0, 0, 1).
  2. Equal to D3DCAPS9.MaxVertexShaderConst (at least 256 for vs_2_0).

Output Registers

Register Name Count R/W Dimension RelAddr Defaults Requires DCL
oPos Position Register 1 W 4 No None No
oFog Fog Register 1 W 1 No None No
oPts Point Size Register 1 W 1 No None No
oD# Color Register; See note 1 2 W 4 No None No
oT# Texture Coordinate Register 8 W 4 No None No

 

Notes:

  • oD0 is the diffuse color output; oD1 is the specular color output.

Vertex Shader Registers